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this document contains information on a new product. specifications and information herein are subject to change without notice . this document provides an overview of the scf5249 coldfire ? processor and general descriptions of scf5249 features and its various modules. the scf5249 was designed as a system controller/decoder for mp3 music players, especially portable mp3 cd players. the 32-bit coldfire core with enhanced multiply accumulate (emac) unit provides optimum performance and code density for the combination of control code and signal processing required for mp3 decode, file management, and system control. low power features include a hardwired cd rom decoder, advanced 0.18um cmos process technology, 1.8v core power supply, and on-chip 96kbyte sram. mp3 decode requires less than 20mhz cpu bandwidth and runs in on-chip sram with external access only for data input and output. the scf5249 is also an excellent general purpose system controller with over 125 dhrystone 2.1 mips @ 140mhz performance at a very competitive price. the integrated peripherals and emac allow the scf5249 to replace both the microcontroller and the dsp in certain applications. most peripheral pins can also be remapped as general purpose i/o pins. scf5249 feature introduction the scf5249 integrated microprocessor combines a version 2 coldfire ? processor core operating at 140mhz with the following modules. ? dma controller with 4 dma channels ? integrated enhanced multiply-accumulate unit (emac) ? 8-kbyte direct mapped instruction cache ? 96-kbyte sram (a 64k and a 32k bank) ? operates from external crystal oscillator ? supports 16-bit wide sdram memories table 1 orderable part numbers orderable part number maximum clock frequency package type operating temperature range scf5249lpv120 120 mhz 144 pin qfp -20 c to 70 c scf5249vf140 140 mhz 160 ball mapbga -20 c to 70 c product brief SCF5249PB/d rev. 2, 12/2003 scf5249 integrated coldfire? microprocessor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2 scf5249 integrated coldfire microprocessor product brief motorola scf5249 block diagram ? serial audio interface which supports iis and eiaj audio protocols ? digital audio transmitter and two receivers compliant with iec958 audio protocol ? cd-rom and cd-rom xa block decoding and encoding function ?two uarts ? queued serial peripheral interface (qspi) (master only) ? two timers ? ide and smartmedia interfaces ? analog/digital converter ? flash memory card interface ?two i 2 c modules ? system debug support ? general purpose i/o pins shared with other functions ? 1.8v core, 3.3v i/o ? 160 pin mapbga package (qualified at 140 mhz) and 144 pin qfp package (qualified at 120 mhz) ?-20 0 c to 70 0 c ambient operating temperature range scf5249 block diagram figure 1 scf5249 block diagram pll frequency synthesizer serial audio interface 3 x i 2 s rx 2 x i 2 stx spdif/ebu transmitter cd rom block decoder encoder cd text interface qspi spdif/ebu receiver ide interface flash media interface i addr gen instr buf i fetch agen& ex dec&sel op 8k byte i-cache b u s c o n t r o l sdram cntr & chip selects timers duart dma m-bus (i 2 c) debug module 96k byte sram general purpose i/o emac coldfire v2 12-bit adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
scf5249 feature details motorola scf5249 integrated coldfire microprocessor product brief 3 scf5249 feature details the primary features of the scf5249 integrated processor include the following: ? coldfire v2 processor core operating at 140mhz C clock-doubled version 2 microprocessor core C 32-bit internal data bus, 16 bit external data bus C 16 user-visible, 32-bit general-purpose registers C supervisor/user modes for system protection C vector base register to relocate exception-vector table C optimized for high-level language constructs ?dma controller C four fully programmable channels: two dedicated to the audio interface module and two dedicated to the uart module (external requests are not supported.) C supports dual- and single-address transfers with 32-bit data capability C two address pointers that can increment or remain constant C 16-/24-bit transfer counter C operand packing and unpacking support C auto-alignment transfers supported for efficient block movement C supports bursting and cycle stealing C all channels support memory to memory transfers C interrupt capability C provides two clock cycle internal access ? enhanced multiply-accumulator unit C single-cycle multiply-accumulate operations for 32 x 32 bit and 16 x 16 bit operands C support for signed, unsigned, integer, and fixed-point fractional input operands C four 48-bit accumulators to allow the use of a 40-bit product C the addition of 8 extension bits to increase the dynamic number range C fast signed and unsigned integer multiplies ? 8-kbyte direct mapped instruction cache C clock-doubled to match microprocessor core speed C flush capability C non-blocking cache provides fast access to critical code and data ? 96-kbyte sram C provides one-cycle access to critical code and data C split into two banks, sram0 (32k), and sram1 (64k) C dma requests to/from internal sram1 supported ? crystal trim C the xtrim output can be used to trim an external crystal oscillator circuit which would allow lock with an incoming iec958 or serial audio signal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4 scf5249 integrated coldfire microprocessor product brief motorola scf5249 feature details ? audio interfaces C iec958 input and output C four serial philips iis/sony eiaj interfaces - one with input and output, one with output only, two with input only (three inputs, two outputs) - master and slave operation ? cd text interface C allows the interface of cd subcode (transmitter only) ? dual universal synchronous/asynchronous receiver/transmitter (dual uart) C full duplex operation C baud-rate generator C modem control signals: clear-to-send (cts) and request-to-send (rts) C dma interrupt capability C processor-interrupt capability ? queued serial peripheral interface (qspi) C programmable queue to support up to 16 transfers without user intervention C supports transfer sizes of 8 to 16 bits in 1-bit increments C four peripheral chip-select lines for control of up to 15 devices C baud rates from 273 kbps to 17.5 mbps at 140mhz C programmable delays before and after transfers C programmable clock phase and polarity C supports wraparound mode for continuous transfers C master mode only ? dual 16-bit general-purpose multimode timers C clock source selectable from external, cpu clock/2 and cpu clock/32. C 8-bit programmable prescaler C 2 timer inputs and 2 outputs C processor-interrupt capability C 14.3 ns resolution with cpu clock at 140mhz ? ide/ smartmedia interface C allows direct connection to an ide hard drive or other ide peripheral ? analog/digital converter C 12-bit resolution C 4 muxed inputs ? flash memory card interface C allows connection to sony memorystick compatible devices C support sd cards and other types of flash media ?dual i 2 c interfaces f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
scf5249 feature details motorola scf5249 integrated coldfire microprocessor product brief 5 C interchip bus interface for eeproms, lcd controllers, a/d converters, keypads C master and slave modes, support for multiple masters C automatic interrupt generation with programmable level ? system debug support C real-time instruction trace for determining dynamic execution path C background debug mode (bdm) for debug features while halted C debug exception processing capability C real-time debug support ? system interface C glueless bus interface with four chip selects and dramc support for interface to 16-bit for dram, sram, rom, flash, and i/o devices - two programmable chip-select signals for static memories or peripherals, with programmable wait states and port sizes. - two dedicated chip selects for 16-bit wide dram /sdram. - cs0 is active after reset to provide boot-up from external flash/rom. ? programmable interrupt controller - low interrupt latency - eight external interrupt requests - programmable autovector generator ? 44 programmable general-purpose inputs* ? 46 programmable general-purpose outputs* * for the 160 mapbga package C ieee 1149.1 test (jtag) module ? clocking C clock-multiplied pll, programmable frequency ? 1.8v core, 3.3v i/o ? 160 pin mapbga package (qualified at 140 mhz) and 144 pin qfp package (qualified at 120 mhz) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6 scf5249 integrated coldfire microprocessor product brief motorola 160 mapbga ball assignments 160 mapbga ball assignments the following signals are not available on the 144 qfp package. note: the 144 qfp part is qualified for 120 mhz operation. the 160mapbga part is qualified for 140 mhz. scf5249 functional overview coldfire v2 core the coldfire processor version 2 core consists of two independent, decoupled pipeline structures to maximize performance while minimizing core size.the instruction fetch pipeline (ifp) is a two-stage pipeline for prefetching instructions. the prefetched instruction stream is then gated into the two-stage operand execution pipeline (oep), which decodes the instruction, fetches the required operands, and then executes the required function. because the ifp and oep pipelines are decoupled by an instruction buffer that serves as a fifo queue, the ifp can prefetch instructions in advance of their actual use by the oep, which minimizes time stalled waiting for instructions. the oep is implemented in a two-stage pipeline featuring a traditional risc data path with a dual-read-ported register file feeding an arithmetic/logic unit (alu). table 2 160 mapbga ball assignments 160 mapbga ball number function gpio e3 cmd_sdio2 gpio34 g4 sdata0_sdio1 gpio54 h3 rsto/sdata2_bs2 k3 a25 gpo8 l4 qspi_cs1 gpio24 l8 qspi_cs3 gpio22 n8 sdram_cs2 gpio7 p9 ebuout2 gpo 37 k11 bufenb2 gpio17 g12 subr gpio 53 f13 sfsy gpio 52 f12 rck gpio 51 e8 sre gpio11 b8 lrck3 gpio 45 e7 swe gpio12 a7 sclk3 gpio 49 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
scf5249 functional overview motorola scf5249 integrated coldfire microprocessor product brief 7 dma controller the scf5249 provides four fully programmable dma channels for quick data transfer. single and dual address mode is supported with the ability to program bursting and cycle stealing. data transfer is selectable as 8, 16, 32, or 128-bits. packing and unpacking is supported. two internal audio channels and the dual uart can be used with the dma channels. all channels can perform memory to memory transfers. the dma controller has a user-selectable, 24- or 16-bit counter and a programmable dma exception handler. external requests are not supported. enhanced multiply and accumulate module (emac) the integrated emac unit provides a common set of dsp operations and enhances the integer multiply instructions in the coldfire architecture. the emac provides functionality in three related areas: 1. faster signed and unsigned integer multiplies 2. new multiply-accumulate operations supporting signed and unsigned operands 3. new miscellaneous register operations multiplies of 16x16 and 32x32 with 48-bit accumulates are supported in addition to a full set of extensions for signed and unsigned integers plus signed, fixed-point fractional input operands. the emac has a single-clock issue for 32x32-bit multiplication instructions and implements a four-stage execution pipeline. instruction cache the instruction cache improves system performance by providing cached instructions to the execution unit in a single clock. the scf5249 processor uses a 8k-byte, direct-mapped instruction cache to achieve 125 mips at 140 mhz. the cache is accessed by physical addresses, where each 16-byte line consists of an address tag and a valid bit. the instruction cache also includes a bursting interface for 16-bit and 8-bit port sizes to quickly fill cache lines. internal 96-kbyte sram the 96-kbyte on-chip sram is split over two banks, sram0 (32k) and sram1 (64k). it provides one clock-cycle access for the coldfire core. this sram can store processor stack and critical code or data segments to maximize performance. memory in the second bank can be accessed under dma. dram controller the scf5249 dram controller provides a glueless interface for up to two banks of dram, each of which can be up to 32 mbytes. the controller supports a 16-bit data bus. a unique addressing scheme allows for increases in system memory size without rerouting address lines and rewiring boards. the controller operates in page mode, non-page mode, and burst-page mode and supports sdrams. system interface the scf5249 provides a glueless interface to 16-bit port size sram, rom, and peripheral devices with independent programmable control of the assertion and negation of chip-select and write-enable signals. the scf5249 also supports bursting roms. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8 scf5249 integrated coldfire microprocessor product brief motorola scf5249 functional overview external bus interface the bus interface controller transfers information between the coldfire core or dma and memory, peripherals, or other devices on the external bus. the external bus interface provides 23 bits of address bus space, a 16-bit data bus, output enable, and read/write signals. this interface implements an extended synchronous protocol that supports bursting operations. serial audio interfaces the scf5249 digital audio interface provides four serial philips iis/sony eiaj interfaces. one interface is a 4-pin (1 bit clock, 1 word clock, 1 data in, 1 data out), the other three interfaces are 3-pin (1 bit clock, 1 word clock, 1 data in or out). the serial interfaces have no limit on minimum sampling frequency. maximum sampling frequency is determined by maximum frequency on bit clock input. this is 1/3 the frequency of the internal system clock. iec958 digital audio interfaces the scf5249 has two digital audio input interfaces, and one digital audio output interface. there are four digital audio input pins, two digital audio output pins. an internal multiplexer selects one of the four inputs to the digital audio input interface. there is one digital audio output interface but it has two iec958 outputs. one output carries the professional c channel, and the other carries the consumer c channel. the rest carry identical data. the iec958 output can take the output from the internal iec958 generator, or multiplex out one of the four iec958 inputs. audio bus the audio interfaces connect to an internal bus that carries all audio data. each receiver places its received data on the audio bus and each transmitter takes data from the audio bus for transmission. each transmitter has a source select register. in addition to the audio interfaces, there are six cpu accessible registers connected to the audio bus. three of these registers allow data reads from the audio bus and allow selection of the audio source. the other three register provide a write path to the audio bus and can be selected by transmitters as the audio source. through these registers, the cpu has access to the audio samples for processing. audio can be routed from a receiver to a transmitter without the data being processed by the core so the audio bus can be used as a digital audio data switch. the audio bus can also be used for audio format conversion. cd-rom encoder/decoder the scf5249 is capable of processing cd-rom sectors in hardware. processing is compliant with cd-rom and cd-rom xa standards. the cd-rom decoder performs following functions in hardware: ? sector sync recognition ? descrambling of sectors ? verification of the crc checksum for mode 1, mode 2 form 1, and mode 2 form 2 sectors ? third-layer error correction is not performed f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
scf5249 functional overview motorola scf5249 integrated coldfire microprocessor product brief 9 the cd-rom encoder performs following functions in hardware: ? sector sync recognition ? scrambling of sectors ? insertion of the crc checksum for mode 1, mode 2 form 1, and mode 2 form 2 sectors. ? third-layer error encoding needs to be done in software. this can use approximately 5-10 mhz of performance for single-speed. dual uart module two full-duplex uarts with independent receive and transmit buffers are in this module. data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. four-byte receive buffers and two-byte transmit buffers minimize cpu service calls. the dual uart module also provides several error-detection and maskable-interrupt capabilities. modem support includes request-to-send (rts ) and clear-to-send (cts ) lines. the system clock provides the clocking function from a programmable prescaler. you can select full duplex, auto-echo loopback, local loopback, and remote loopback modes. the programmable dual uarts can interrupt the cpu on various normal or error-condition events. queued serial peripheral interface qspi the qspi module provides a serial peripheral interface with queued transfer capability. it supports up to 16 stacked transfers at a time, making cpu intervention between transfers unnecessary. transfers of up to 37 mbits/second are possible at a cpu clock of 140 mhz. the qspi supports master mode operation only. timer module the timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer for use in any of three modes: 1. timer capture. this mode captures the timer value with an external event. 2. output capture. this mode triggers an external signal or interrupts the cpu when the timer reaches a set value 3. event counter. this mode counts external events. the timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is derived from the system clock. in addition to the 1 and 16 clock derived from the bus clock (cpu clock / 2), the programmable timer-output pins either generate an active-low pulse or toggle the outputs. ide and smartmedia interfaces the scf5249 system bus allows connection of an ide hard disk drive and smartmedia flash card with a minimum of external hardware. the external hardware consists of bus buffers for address and data and are intended to reduce the load on the bus and prevent sdram and flash accesses to propagate to the ide bus. the control signals for the buffers are generated in the scf5249. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10 scf5249 integrated coldfire microprocessor product brief motorola scf5249 functional overview analog/digital converter (adc) the four channel adc is a based on the sigma-delta concept with 12-bit resolution. the digital portion of the adc is provided internally. the analog voltage comparator must be provided externally as well as an external integrator circuit (resistor/capacitor) which is driven by the adc output. a software interrupt is provided when the adc measurement cycle is complete. flash memory card interface the interface is sony memorystick and securedigital compatible. however, there is no hardware support for magicgate. i 2 c module the two-wire i 2 c bus interface, which is compliant with the philips i 2 c bus standard, is a bidirectional serial bus that exchanges data between devices. the i 2 c bus minimizes the interconnection between devices in the end system and is best suited for applications that need occasional bursts of rapid communication over short distances among several devices. bus capacitance and the number of unique addresses limit the maximum communication length and the number of devices that can be connected. chip-selects two programmable chip-select outputs provide signals that enable glueless connection to external memory and peripheral circuits. the base address, access permissions and automatic wait-state insertion are programmable with configuration registers. these signals also interface to 16-bit ports. cs0 is active after reset to provide boot-up from external flash/rom. gpio interface a total of 44 general purpose inputs and 46 general purpose outputs are available. these are multiplexed with various other signals. eight of the gpio inputs have edge sensitive interrupt capability. interrupt controller the interrupt controller provides user-programmable control of a total of 57 interrupts. there are 49 internal interrupt sources. in addition, there are 8 gpios where interrupts can be generated on the rising or falling edge of the pin. all interrupts are autovectored and interrupt levels are programmable. jtag to help with system diagnostics and manufacturing testing, the scf5249 includes dedicated user-accessible test logic that complies with the ieee 1149.1a standard for boundary scan testability, often referred to as joint test action group, or jtag. for more information, refer to the ieee 1149.1a standard. motorola provides bsdl files for jtag testing. system debug interface the coldfire processor core debug interface supports real-time instruction trace and debug, plus background-debug mode. a background-debug mode (bdm) interface provides system debug. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general device information motorola scf5249 integrated coldfire microprocessor product brief 11 in real-time instruction trace, four status lines provide information on processor activity in real time (pst pins). a four-bit wide debug data bus (ddata) displays operand data and change-of-flow addresses, which helps track the machines dynamic execution path. crystal and on-chip pll typically, an external 16.92 mhz or 33.86 mhz clock input is used for cd r/w applications, while an 11.2896 mhz clock is more practical for portable cd player applications. however, the on-chip programmable pll, which generates the processor clock, allows the use of almost any low frequency external clock (5-35 mhz). two clock outputs (mclk1 and mclk2) are provided for use as audio master clock. the output frequencies of both outputs are programmable to fxtal, fxtal/2, fxtal/3, and fxtal/4. the fxtal/3 option is only available when the 33.86 mhz crystal is connected. the scf5249 supports vco operation of the oscillator by means of a 16-bit pulse density modulation output. using this mode, it is possible to lock the oscillator to the frequency of an incoming iec958 or iis signal. the maximum trim depends on the type and design of the oscillator. typically a trim of +/- 100 ppm can be achieved with a crystal oscillator and over +/- 1000 ppm with an lc oscillator. general device information the scf5249 is available in a 160-pin map bga package, or a 144-pin qfp package. documentation table 3 lists the documents that provide a complete description of the scf5249 and are required to design properly with the part. documentation is available from a local motorola distributor, a motorola semiconductor sales office, a motorola literature distribution center, or through the motorola dsp home page on the internet; http://e-www.motorola.com/ (the source for the latest information). table 3 scf5249 documentation document name description order number cfprm/d coldfire family programmers reference manual cfprm/d coldfire2um version 2/2m coldfire core processor users manual coldfire2um/d coldfire2umad version 2/2m coldfire core processor users manual addendum coldfire2umad/d scf5249um scf5249 users manual scf5249um/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors SCF5249PB/d rev. 2 12/2003 information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. typical parameters that may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola inc. 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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